Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET) has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, it suffers from problems related to the inability of the gate to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. These short channel effects become particularly pronounced as device geometries shrink to 0.13 microns and below. One of the primary means by which short-channel effects are kept under control is the downscaling of the gate dielectric thickness in conjunction with transistor size reduction.
The scaling trend of the MOSFET gate dielectric thickness is shown in FIG. 1. The projected range of the equivalent silicon oxide (SiO2) thickness tox,eq for high-performance logic applications is plotted using bars (plotted against the left axis). For example, in the year 2016, tox,eq is expected to be less than 6 angstroms for high performance logic applications. The supply voltage VDD is also indicated in FIG. 1. Assuming the most conservative tox,eq scaling, i.e., largest value for each bar, the gate leakage current density through SiO2 is calculated and plotted as the solid line 2 (plotted against the right axis). Even with conservative tox,eq scaling, excessive gate leakage prohibits continued gate dielectric scaling using SiO2. Under current process technologies, ultra-thin films are in the range of 2 angstroms to 20 angstroms. Preferably, ultra-thin SiO2 films are less than 10 angstroms. Such ultra-thin films not only lead to excessive leakage, but also aggravate the problems of poly-silicon (poly-Si) gate depletion, gate dielectric integrity, and gate dopant penetration to the channel region.
So-called high-k gate dielectrics have been proposed because of their improved gate leakage properties. High-k gate dielectrics may be suitable candidates, examples of which include (but are not limited to) metallic oxides such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), and hafnium oxide (HfO2), silicates such as ZrSiO4, and aluminates such as lanthanum aluminate. Many high-k gate dielectrics in direct contact with the silicon substrate have poorer interface properties than SiO2 or SiON on silicon. Therefore, an interfacial SiO2 or SiON layer is sometimes inserted below the high-k gate dielectric to obtain reasonable carrier mobilities in the transistor channel.
U.S. Pat. No. 6,015,739 describes a method for the fabrication of a gate dielectric stack where a dielectric film with a relative dielectric permittivity or relative permittivity of 20–200 overlies a silicon nitride film over a native oxide layer formed on a semiconductor substrate. U.S. Pat. No. 6,448,127, describes a method for the formation of a high-k gate dielectric overlying silicon oxide. The relative permittivity of a material is the ratio of the electric permittivity of the material to the permittivity of free space ε0. The permittivity of free space is 8.85×10−12 F/m.
The gate dielectric stack structures such as those described above have limited scalability to ultra-thin equivalent SiO2 thicknesses below approximately 7 angstroms for high performance applications. Although transistors with high-k/SiO2 or high-k/SiON stack gate dielectrics provide improved gate leakage current performance, they often do so at the sacrifice of switching speed. As such, the high-k devices are not a satisfactory solution in applications where speed performance is important.
Other attempts at improving device performance have involved the provision of transistors on the same chip with differing gate oxides. Examples include U.S. Pat. No. 5,668,035 issued to Fang et al., U.S. Pat. No. 6,030,862 issued to Kepler, U.S. Pat. No. 6,265,325 issued to Cao et al., U.S. Pat. No. 6,383,861 issued to Gonzalez et al., and U.S. Pat. No. 6,168,958 issued to Gardner et al. Hence, a need exists to overcome the various shortcomings in the prior art for chips having regions where gate leakage current is more important and regions where switching speed is more important.